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2010-2012 Microchip Technology Inc.

DS39977F-page 217

PIC18F66K80 FAMILY

FIGURE 14-4:

TIMER1 GATE COUNT ENABLE MODE

14.8.2

TIMER1 GATE SOURCE

SELECTION

The Timer1 gate source can be selected from one of

four sources. Source selection is controlled by the

T1GSSx (T1GCON<1:0>) bits (see Table 14-4).

TABLE 14-4:

TIMER1 GATE SOURCES

The polarity for each available source is also selectable,

controlled by the T1GPOL bit (T1GCON<6>).

14.8.2.1

T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

14.8.2.2

Timer2 Match Gate Operation

The TMR2 register will increment until it matches the

value in the PR2 register. On the very next increment

cycle, TMR2 will be reset to 00h. When this Reset

occurs, a low-to-high pulse will automatically be gener-

ated and internally supplied to the Timer1 gate circuitry.

The pulse will remain high for one instruction cycle and

will return back to a low state until the next match.

Depending on T1GPOL, Timer1 increments differently

when TMR2 matches PR2. When T1GPOL = 1, Timer1

increments for a single instruction cycle following a

TMR2 match with PR2. When T1GPOL = 0, Timer1

increments continuously except for the cycle following

the match when the gate signal goes from low-to-high.

14.8.2.3

Comparator 1 Output Gate

Operation

The output of Comparator 1 can be internally supplied

to the Timer1 gate circuitry. After setting up

Comparator 1 with the CM1CON register, Timer1 will

increment depending on the transitions of the

CMP1OUT (CMSTAT<6>) bit.

14.8.2.4

Comparator 2 Output Gate

Operation

The output of Comparator 2 can be internally supplied

to the Timer1 gate circuitry. After setting up

Comparator 2 with the CM2CON register, Timer1 will

increment depending on the transitions of the

CMP2OUT (CMSTAT<7>) bit.

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1

N + 1

N + 2

N + 3

N + 4

T1GSS<1:0>

Timer1 Gate Source

Timer1 Gate Pin

TMR2 to Match PR2

(TMR2 increments to match PR2)

Comparator 1 Output

(comparator logic high output)

Comparator 2 Output

(comparator logic high output)

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